Switching-type regulators (aka switched-mode power supplies or switch regulators) are electronic power supplies that typically utilize a high current switch (e.g., a MOSFET) along with an oscillator and pulse width modulator (PWM) to convert the voltage and current characteristics of a DC supply voltage in order to supply a load circuit with either a stepped-up (increased) voltage/current or a stepped-down (decreased) voltage/current. The oscillator, PWM and switch are connected in a closed loop system with the loop feedback usually compared with a reference voltage, and the result is modulated by the PWM, which in turn controls the switch's duty cycle to provide a regulated direct current (DC) voltage output signal. Buck converters are switching-type voltage regulators in which the output voltage is substantially lower (“stepped down”) than the source (input) voltage. In contrast, up-converters are switching-type voltage regulators in which the regulated output exceeds the input supply voltage, and positive-to-negative or negative-to-positive polarity converters are switching-type voltage regulators in which the regulated output is inverted. In terms of power supply efficiency switching-type regulators can operate at about 90% or better.
FIG. 6 is a simplified circuit diagram showing an exemplary conventional buck converter 50 including an error amplifier 51, a pulse width modulator (PWM) circuit 52, an oscillator 53, a pre-driver (amplifier) 54, a power transistor 55, and an output inductor LOUT. Error amplifier 51 compares a reference voltage VREF and a feedback signal VFB, and generates an output signal VEA-OUT that is applied to PWM 52. In general, PWM circuit 52 compares error amplifier output signal VEA-OUT with an oscillating ramp signal VOSC-RAMP supplied by oscillator 53, and produces a square wave signal VPULSE having a duty cycle whose instantaneous value is related to the voltage level of error amplifier output signal VEA-OUT. In current mode convertors, a first feedback circuit adds an additional voltage VILOUT, which is proportional to inductor current ILOUT, to oscillator ramp signal VOSC-RAMP such that the gradient of oscillating ramp signal VOSC-RAMP is determined not only by oscillator 53, but is also made proportional to the inductor current ILOUT by way of additional voltage VILOUT. Square wave signal VPULSE is amplified by pre-driver 54 to generate a square-wave gate voltage VGN, which is made up of a series of voltage pulses VGN-P that are applied to the gate of power transistor 55. Power transistor 55 is turned on and off in accordance with the duty cycle of gate voltage VGN, thereby generating an inductor voltage VLOUT at node N that toggles with the same frequency (duty cycle) as square wave signal VPULSE and square-wave gate voltage VGN. Inductor voltage VLOUT is passed through output inductor LOUT, thereby generating regulated output voltage VOUT that is supplied to a target load circuit L, which for simplicity is represented by a capacitor CL and a resistor RL. A portion of regulated output voltage VOUT is fed back as feedback signal VFB to error amplifier 51 via a suitable second feedback circuit (e.g., the divider formed by resistors R1 and R2), whereby the duty cycle of PWM circuit 52 is maintained at a level that generates the duty cycle needed to produce the desired regulated voltage VOUT.
A problem associated with conventional buck converters is voltage overshoot and inductor current at start-up (i.e., when power is initially supplied to buck converter 50). Before start-up, load capacitance CL is fully discharged, and output voltage VOUT is zero. At start-up (e.g., when power VDD is initially applied), because output voltage VOUT is initially 0V, reference voltage VREF will dominate the operation of error amplifier 51, thus causing it to generate output signal VEA-OUT that maximizes the duty cycle of PWM circuit 52 in an effort to charge load capacitor CL as rapidly as possible. The resulting surge can damage power transistor 55 and typically overshoots the desired output voltage, possibly overloading the input supply and/or damaging load L. The surge also generates a high inrush current via output inductor LOUT.
FIG. 7(A) is a timing diagram illustrating a generalized conventional “soft-start” (SS) process, which is used to address the start-up overshoot problem associated with conventional buck converters by causing output voltage VOUT to gradually rise from 0V to the desired nominal level during a soft-start period prior to normal operation. The basic method for implementing a conventional SS process is to control the error amplifier output signal VEA-OUT such that it increases gradually at start-up, which causes the duty cycle of PWM 52 to gradually increase, which in turn limits the amount of current passed by power transistor 55 to load L via output inductor LOUT. As indicated in FIG. 7(A), the gradual increase of error amplifier output signal VEA-OUT is typically achieved by causing reference voltage VREF to slowly increase from 0V to a normal operating level (e.g., over a 600 micro-second period starting at initial start-up time t0), thereby limiting the output of error amplifier 51 according to the slowly increasing reference voltage VREF. The resulting gradual increase of error amplifier output signal VEA-OUT prevents significant load surge by causing output voltage VOUT to gradually increase. At the end of the soft-start period (i.e., at the beginning of “normal” converter operation), reference voltage VREF is maintained at its predetermined fixed value, and error amplifier output signal VEA-OUT is adjusted in accordance with the fed back portion of output voltage VOUT in the manner described above.
FIG. 7(B) illustrates an “initial SS phase” problem associated the conventional basic soft-start approach illustrated in FIG. 7(A) that arises while error amplifier output signal VEA-OUT is “out of dynamic range” (i.e., too low), which prevents buck converter 50 from starting properly. Referring to FIG. 6, PWM 52 generates output voltage VPULSE (and, effectively, gate voltage VPULSE/VGN) having pulse widths that are based on a duty cycle determined by a comparison between error amplifier output signal VEA-OUT and oscillating ramp signal VOSC-RAMP (plus the additional voltage VILOUT, which is proportional to inductor current ILOUT). As indicated in FIG. 7(B), the “initial SS phase” problem arises because, while error amplifier output signal VEA-OUT gradually increases from 0V as described above, oscillating ramp signal VOSC-RAMP starts at a voltage higher than 0V at time t0 due to some voltage shift proportional to the inductor current is immediately added when the initial SS phase starts at time t0. That is, during the “initial SS phase” (i.e., between time t0 and t2, while error amplifier output signal VEA-OUT is still very low), oscillating ramp signal VOSC-RAMP remains above error amplifier output signal VEA-OUT at the beginning of every clock cycle, and therefore the duty cycle during the initial SS phase is “0” (i.e., voltages VPULSE/VGN remain at 0V). Theoretically, the initial SS phase duty cycle will remain “0” while error amplifier output signal VEA-OUT remains “out of dynamic range” (i.e., below some minimal level, e.g., voltage VMIN, shown in FIG. 7(B)). That is, until error amplifier output signal VEA-OUT reaches minimum voltage VMIN (e.g., at time t2 in FIG. 7(B)), the feedback loop of buck converter 50 would remain open and uncontrollable (i.e., buck converter 50 would be operating as an open-loop circuit). This open-loop (“0” duty cycle) condition occurs before feedback signal VFB is established and stabilized, which is required for error amplifier 50 to function properly, and cannot be prevented.
FIGS. 8(A) and 8(B) are diagrams illustrating a conventional “minimum initial duty cycle” approach that addresses the “0” duty cycle problem and produces output voltage VOUT for the required minimum “on” time by “forcing” a minimum duty cycle. Specifically, PWM 52 (see FIG. 6) is configured in the conventional “minimum initial duty cycle” approach to generate voltages VPULSE/VGN with a minimum duty cycle DMIN determined, for example, by dividing the required minimum “on” time by the normal system operating period set by oscillator 53. For example, if the required minimum “on” time for a given circuit is 100 nanoseconds and the system operating frequency is 1 Mhz, then the minimum duty cycle DMIN would be 100 ns/1 μs, or 0.1. Using this example, as illustrated in FIG. 8(B), voltages VPULSE/VGN are therefore generated as 100 nanosecond pulses occurring every 1 μs (e.g., at the beginning of each pulse of oscillator signal VOSC-RAMP) starting at time t0 and continuing through the initial SS phase (e.g., until error amplifier output signal VEA-OUT reaches minimum voltage VMIN needed for normal SS operations). Referring back to FIG. 8(A), starting at time t2 the duty cycle is then gradually increased to a final duty cycle DFIN at the end of the SS process, and as shown in FIG. 8(B) voltages VPULSE/VGN are generated as increasingly longer pulses as the duty cycle increases. At the end of the SS process, the duty cycle is controlled by PWM 52 in accordance with the comparison between oscillating ramp signal VOSC-RAMP and error amplifier output signal VEA-OUT in the manner described above.
A further problem with the conventional “forced minimum duty cycle” approach described above with reference to FIGS. 8(A) and 8(B) is that it can still cause overshoot and inrush during the early portion of the initial SS phase. That is, even though the forced minimum duty cycle causes power transistor 55 to pass a limited amount of current to node N (FIG. 6), output voltage VOUT will increase to the voltage level of voltage VLOUT multiplied by the minimum duty cycle (i.e., VOUT equals system voltage VDD multiplied by duty cycle DMIN), which can lead to overshoot and inrush at the beginning of the initial SS phase. Specifically, because every PWM/gate voltages VPULSE/VGN associated with minimum duty cycle DMIN is at system voltage VDD during the initial SS phase, output voltage VOUT can be caused to undergo a rapid rise that overshoots the maximum load operating voltage and damages the load circuitry.
FIGS. 9(A), 9(B) and 9(C) illustrate a conventional “gradually increasing duty cycle” approach to address the additional start-up problem explained above with reference to FIG. 8(B). As indicated in FIG. 9(A), this approach involves causing oscillator 53 to generate oscillator ramp signal VOSC-RAMP such that it starts at a relatively low frequency (e.g., starting with a period that is much larger than 1 μs), and gradually increases until it reaches the normal system operating frequency (e.g., 1 Mhz) at a time t1. FIG. 9(B) depicts PWM/gate voltages VPULSE/VGN, which is made up of pulses generated in accordance with the gradually increasing frequency of oscillator ramp signal VOSC-RAMP, whereby the period between pulses immediately after time t0 is much larger than 1 μs, and the period between pulses gradually reduces to 1 μs at time t1. Note that each pulse of PWM/gate voltages VPULSE/VGN is minimized (e.g., 100 nanoseconds). As such, as illustrated in FIG. 9(C), the effective duty cycle associated with PWM/gate voltages VPULSE/VGN gradually increases from a low number to the desired minimum duty cycle DMIN (e.g., 0.1) between time t0 and t1, and then increases as described above at time t2, thereby causing output voltage VOUT to rise at a much lower rate that prevents overshoot and inrush during the initial SS phase. Accordingly, the conventional “gradually increasing duty cycle” approach generates a gradually increasing duty cycle by causing oscillator 53 to generate oscillating ramp signal VOSC-RAMP at a gradually increasing rate, thereby both providing the necessary minimum “on” time to establish current replica stabilization, and also causing output voltage VOUT to increase at a slower rate that avoids overshoot and inrush during the initial SS phase.
A problem with the above-mentioned prior art “gradually increasing duty cycle” approach is that, by generating oscillating ramp signal VOSC-RAMP with a gradually increasing frequency during the initial SS phase, oscillator 53 can only be used to drive a single buck/boost converter circuit. In the example described above, once the initial SS phase is completed and buck converter 50 is operating normally, oscillator signal VOSC-RAMP is stabilized at the constant system operating frequency (e.g., 1 Mhz). Although this approach is acceptable when oscillator 53 provides oscillator ramp signal VOSC-RAMP to only one buck/boost converter, in many integrated circuits a single oscillator is used to drive two or more buck/boost converters in order to minimize chip area, and to synchronize the convertors' switching times during the normal operation in such a way that their power switches will never open/close in the same time to reduce the system noise and its effects. In contrast, when two different oscillators are used to drive two different converters, then the convertors are not synchronized, and simultaneous opening/closing of their power-switches can't be avoided. When a single oscillator is used to drive two or more buck/boost converters, the two or more buck/boost converters are initiated (started up) at different times during the start-up process for synchronization reasons. In this instance, in order to utilize the oscillator 53 to “soft-start” a second converter, it would be necessary to effectively “stop” and then restart oscillator 53 so that oscillator signal VOSC-RAMP rises from zero to minimum duty cycle DMIN as described above. However, restarting oscillator 53 would create a conflict in that it would disrupt the operation of buck converter 50, which could cause system failure. Accordingly, the conventional “gradually increasing duty cycle” solution can only be reliably used when each buck/boost converter circuit is provided its own oscillator, which increases the chip area required for implementing multiple buck/boost converters, and may lead to synchronization problems.
What is needed is a soft-start circuit in which an oscillator ramp signal is shared by multiple (buck or boost) DC-DC switching regulators started in sequence (i.e., one at a time) without having to restart the oscillator. What is also needed is method for performing a soft-start operation in which multiple switching regulators utilize a ramp signal generated by a single oscillator.